FIG. 1 shows an example of a discrete RF-LDMOS (Laterally Diffused Metal Oxide Semiconductor) power amplifier transistor module 1. The module comprises a RF transistor die 2, and a matching network consisting of bond wires 3a, 3b and two discrete capacitors 4a, 4b. The gate and drain are coupled to terminals 5 and 6 respectively via bond wires. The source is coupled to mounting plate 7 via conductive solder between the terminal 7 and the silicon substrate. The mounting plate 7 thus acts as the source terminal.
The RF-LDMOS die is a very specialized transistor where a lot of special measures are taken to optimize its performance with respect to power efficiency (i.e. the ratio between consumed DC power and delivered RF power). Such a transistor has for instance been described in WO 2009/128035.
At a typical operating frequency of 2 GHz, the input and output impedances of this transistor contain resistive and reactive components. The reactive component is usually capacitive. The reactive component causes a reactive current to flow, which can cause losses due to parasitic resistances in the transistor module 1. These losses reduce the power efficiency of the transistor. Also, the reactive currents do not contribute to the output power.
The purpose of the inductance Li, which is provided by bond wires 3b between the drain bonding pads on the transistor die 2 and the capacitor 4b, is to introduce an appropriate amount of inductive current, which should, at the intended operating frequency, approximately compensate the capacitive current. The discrete decoupling capacitance Cpo (i.e. capacitor 4b) is needed to ensure that the drain of the RF-LDMOS die 2 can be biased with the desired DC voltage. When decoupling is the only desired function of this capacitance, its value should be fairly large, so that at the operating frequency of the transistor it has a low impedance compared to the impedance of the bond wire L.
The drain of the transistor 2 is connected to the drain contact 6 of the package with bond wires, which together have inductance Ld. This compensation scheme for the reactive output current brings the output impedance to a more practical level. Although very effective, it only works at a limited frequency range and is therefore mostly suitable for narrow-band applications.
At the input, a different matching network topology has been used. Here again the purpose of the inductance Lg1 is to compensate the capacitive component of the input impedance at the intended operating frequency, and thus bring the input impedance to a more practical level. However, now this impedance matching is done in two stages, the first stage being formed by Lg2 and Cpr (i.e. capacitor 4a), and the second stage being formed by Lg1. This topology acts as a low-pass filter and generally has a wider bandwidth than the output matching network.
The two impedance matching topologies shown here are only two of the many solutions available to those skilled in the art, which all aim to compensate reactive parts of impedances and/or transform the remaining resistive impedances to more practical levels.
Since the reactive currents in the transistor can be very high, the resistive losses in the input and output matching networks can be significant. Any resistive losses in the input matching network will reduce the power gain, and any resistive losses in the output matching network will reduce the power gain and also the power efficiency and the maximum power available from the device.
Contrary to what might be expected at first glance, the RF currents only flow in the surface of the transistor module 1 parts due to the skin effect. In the metal parts this skin depth is about 2 μm at a frequency of 2 GHz. In the silicon die 1, this skin depth is about 100 μm at the same frequency. The resistance seen by the currents flowing in the transistor module 1 is the skin resistance, which is the specific bulk resistance divided by the skin depth.
In the module 1 shown in FIG. 1, the resistance seen by the inductive compensation current is the sum of the bond wire resistance (which is given by the product of the skin resistance of the bond wire material and the bond wire length divided by the bond wire circumference (π×the bond wire diameter) and the number of parallel bond wires), the equivalent series resistance (ESR) of the parallel capacitor, the skin resistance of the mounting plate (which is roughly the product of the skin resistance of the mounting plate material and the die to parallel capacitor separation divided by the die and parallel capacitor width), and the skin resistances of the sides of the transistor's die 2 and parallel capacitor 4a, 4b chips (which is the product of the skin resistance of the conductive silicon and the chip height divided by the chip width). For a typical chip height of 175 μm, the chip side resistances may well provide over 75% of the total compensation-circuit series resistance and reduce the Q-factor of the compensation circuit from 80 to below 20.
The undesirable chip-side resistive losses could be eliminated by integrating the parallel capacitors with the RF-LDMOS transistor on a single die. However, the distance between the capacitors 4a, 4b and the die 2 cannot be substantially reduced by integration since the bond wires need to be sufficiently long to provide high Q-factor inductances. Therefore, integration would not provide the usual cost benefits, since the required amount of silicon area is actually increased, which would offset the cost savings of not having to use a multi-chip module.